Ive got a board that needs a new 007644 custom chip.
While im waiting to find a new one I thought I would investigate how this chip actually works.
Pin 1 = SEL – changes whether the Q outputs require a rising edge clock or not.
Pin 2 = OEY – Output enable for the Y outputs else they are inputs. Active LOW
Pin 21 = OEQ – Output enable for the Q (clocked) outputs else they are inputs. Active LOW
Pin 12 = CLK – Clock input
Pins 3-10 = Y outputs – normal outputs. If OEY is LOW these pins become outputs mirroring the state of the Q input pins. SEL and CLK pins are not used in this mode.
Pins 13-20 = Q outputs – clocked outputs. If OEQ is LOW these pins become outputs. If SEL is HIGH and CLK is HIGH these outputs will mirror the state of the Y inputs. If SEL is LOW then the outputs will only change state on a rising edge CLK.
Pretty simple and should be easy to implement in a small CPLD if ever required (next project???)