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PCB

PLD's

PLD Information Credits Download Pictures
Dump Method Target Device Location ID Status Creator(s) Tester(s) Files View
Bruteforced GAL16V8 6J (lower PCB) Tested Caius Caius JEDEC
Bruteforced GAL16V8 6K (lower PCB) Tested Caius Caius JEDEC
Modified GAL22V10 A1 (upper PCB) Tested Caius Caius JEDEC
For A1, tie pin 10 to 12 when install chip in socket. Original device was a PAL16L8 but unable to fit equations into device